Title:
データ取得システムおよび方法の平均クロック調整
Document Type and Number:
Japanese Patent JP6865222
Kind Code:
B2
Abstract:
A system and method for adjusting a clock signal of a seismic data acquisition system. The system includes a data acquisition device having an oscillator that generates a clock signal; a clock adjustment module that receives a time reference signal and the clock signal and outputs an adjusted clock signal; and an analog-to-digital convertor configured to transform analog data into digital data having a sampling rate (FDATA). A sampling frequency (fADC) of the analog-to-digital convertor is selected to be at least twice the sampling rate (FDATA).
Inventors:
Senegal Emanuel
Application Number:
JP2018531096A
Publication Date:
April 28, 2021
Filing Date:
December 14, 2016
Export Citation:
Assignee:
Cell cell
International Classes:
G01V1/22
Domestic Patent References:
| JP2004093411A | ||||
| JP11264849A | ||||
| JP2001235567A | ||||
| JP2001215283A | ||||
| JP2002101079A |
Foreign References:
| US20070276891 | ||||
| US20100198561 |
Attorney, Agent or Firm:
Shinei Patent Office