Title:
メモリアクセス動作中に、メモリの複数のメモリプレーンに同時にアクセスするための装置および方法
Document Type and Number:
Japanese Patent JP6931674
Kind Code:
B2
Abstract:
Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.
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Inventors:
Lagede, Shantanuar.
Caravado, Planahu
Toru Tanzawa
Caravado, Planahu
Toru Tanzawa
Application Number:
JP2019105469A
Publication Date:
September 08, 2021
Filing Date:
June 05, 2019
Export Citation:
Assignee:
Micron Technology, Ink.
International Classes:
G11C16/26; G11C11/56; G11C16/08; G11C16/30
Foreign References:
| WO2015025357A1 | ||||
| US20100124107 | ||||
| US20100329047 | ||||
| US20070047300 |
Attorney, Agent or Firm:
Hiroyoshi Aoki
Amada Masayuki
Yoshiyuki Osuga
Nomura Yasuhisa
Amada Masayuki
Yoshiyuki Osuga
Nomura Yasuhisa