Document Type and Number:
Japanese Patent JPH0511450
Kind Code:
B2
Abstract:
In a line equalizer responsive to an input signal of a variable data rate for producing an equalizer output signal, a control circuit (12) supplies an equalizer circuit (11) with a selection signal (SEL) which is determined by the data rate and an output level of the equalizer output signal to select one of frequency-gain characteristics that is matched with a line loss characteristic of a line. The equalizer circuit is implemented by a switched capacitor circuit and samples the input signal by a clock signal (CK) a clock frequency of which is varied by a clock signal controller (51) in consideration of the data rate. An additional equalizer circuit may be connected in cascade to the equalizer circuit and controlled by an additional control signal determined by the data rate and the output level. In this event, the selection signal may be determined only by the output level with the clock signal left out of consideration.
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Inventors:
NAKAYAMA KENJI
TAKEUCHI YAYOI
TAKEUCHI YAYOI
Application Number:
JP18481584A
Publication Date:
February 15, 1993
Filing Date:
September 04, 1984
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H03H19/00; H04B3/14; H04L25/03; H04L25/04
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