Title:
フィルタ回路及びこれを用いた通信用半導体装置
Document Type and Number:
Japanese Patent JP5038069
Kind Code:
B2
Abstract:
The present invention intends to provide a filter circuit in which an area occupied by the circuit can be reduced by suppressing the scale of its circuit configuration while a predetermined vicinity disturbance wave rejection ratio is maintained and a communication semiconductor device using the same, the filter circuit filtering an analog signal and including a voltage/current conversion circuit for converting the analog signal from voltage to current, and a capacitor array which executes signal processing by charging/discharging the current converted by the voltage/current conversion circuit to/from plural capacitors, the capacitor array being so constructed that the plural capacitors are divided to plural stages so that signals averaged by the capacitor on a preceding stage are accumulated in the capacitor on a next stage successively.
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Inventors:
Tomohiro Sano
Takaya Maruyama
Hisayasu Sato
Takaya Maruyama
Hisayasu Sato
Application Number:
JP2007230985A
Publication Date:
October 03, 2012
Filing Date:
September 06, 2007
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H03H19/00; H03H11/04; H04B1/16
Domestic Patent References:
| JP3244211A |
Other References:
浜田菜穗、外3名,デシメーション型サンプリングフィルタの小型化の検討,電子情報通信学会技術報告 ソフト無線,日本,社団法人電子情報通信学会,2007年 7月19日,vol.107, No.162,p.145-150
Attorney, Agent or Firm:
Yoshitake Hidetoshi
Takahiro Arita
Takahiro Arita