Title:
【発明の名称】垂直導体の間に接点領域を形成する方法
Document Type and Number:
Japanese Patent JPH10507879
Kind Code:
A
Abstract:
A method of forming a contact area between two vertical structures. A first layer of material conforming to an extending between vertical sidewalls is covered with a mask layer. The mask layer is patterned and etched to remove the horizontal region of the mask layer between the vertical sidewalls, thereby exposing the first layer of material at the desired location of the contact area, while retaining at least a portion of the vertical regions of the mask layer. Using the remaining vertical regions of the mask layer as etch mask, the exposed portions of the first layer are then etched away to form the contact area. Another aspect of the invention provides a method of making a DRAM that utilizes a capacitor insulating layer over the capacitor second conductor (or cell poly) to self-align the bit line contact to the capacitor second conductor. In accordance with this aspect of the invention, a capacitor is formed over a semiconductor wafer. The capacitor includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. A capacitor insulating layer is formed on the second conductor. The capacitor insulating layer is patterned and etched to expose portions of the second conductor at the desired location of the bit line contact. Then, using the capacitor insulating layer as a hard mask, the exposed portions of the second conductor are etched away in the area in which the bit line contact will subsequently be formed.
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Inventors:
Figra, Thomas A.
Prowl, Kirk Dee.
Prowl, Kirk Dee.
Application Number:
JP51551396A
Publication Date:
July 28, 1998
Filing Date:
November 07, 1995
Export Citation:
Assignee:
Micron, Technology, Incorporated
International Classes:
H01L21/768; H01L21/8242; H01L27/108; (IPC1-7): H01L27/108; H01L27/108; H01L21/8242; H01L21/768
Attorney, Agent or Firm:
Atsushi Nakajima (2 outside)