Title:
【発明の名称】発生する確率の低減されたパンチスルーと、低いRDSonとを備えた溝型電界効果トランジスタ
Document Type and Number:
Japanese Patent JPH10507880
Kind Code:
A
Abstract:
To reduce susceptibility to punchthrough, the channel region of the P body region of a trench field effect transistor is formed in a layer of lightly doped epitaxial silicon. As a result, the channel region has less counterdoping from the background epitaxial silicon and has a greater net P type dopant concentration. Due to the higher net dopant concentration of the P body region, the depletion regions on either side of the P body region expand less far inward through the P body region at a given voltage, thereby rendering the transistor less susceptible to source-to-drain punchthrough. To maintain a low RDSon, the relatively high conductivity of an accumulation region formed along a sidewall of the trench of the transistor when the transistor is on is used to form a conductive path from the channel region to an underlying relatively highly conductive layer upon which the lightly doped epitaxial layer is formed. This underlying relatively highly conductive layer may, for example, be either substrate or a more highly doped epitaxial silicon layer.
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Inventors:
Xie, Fu-Yu Yan
Chung, Mike F
Chung, Mike F
Application Number:
JP52427696A
Publication Date:
July 28, 1998
Filing Date:
February 07, 1996
Export Citation:
Assignee:
SILICONIX INCORPORATED
International Classes:
H01L21/336; H01L29/423; H01L29/78; H01L29/08; (IPC1-7): H01L29/78; H01L29/78
Attorney, Agent or Firm:
Yoichi Oshima (1 outside)