Document Type and Number:
Japanese Patent JPS5179524
Kind Code:
A
Abstract:
1534521 FET circuits HITACHI Ltd 11 Dec 1975 [6 Jan 1975] 50854/75 Heading H3T A circuit for using a high voltage as input to a MISFET circuit, e.g. an inverter M3, M4 comprises an enhancement MISFET M1 connected between the input and a lower voltage supply V GG and a second MISFET M2 in series between the input and the gate of the inverter driver M4. When the high voltage is applied to the input, M1 turns off and M2 limits the voltage on the gate of M4 to (V GG -Th) or (V GG + Th) where Th is the threshold voltage according to whether M2 is of enhancement or depletion type. Resistors R1, R2 may be provided to protect the MISFETS gate insulation from breakdown by interference voltages. As described the invention is used in a desk-top calculator in which the high-voltage supply to a display 2 is connected to a key switch 3 for connection to the input.
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Inventors:
KAWAGOE KOJI
NOMYA HIROYASU
NOMYA HIROYASU
Application Number:
JP10375A
Publication Date:
July 10, 1976
Filing Date:
January 06, 1975
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H03M11/20; G06F3/023; H03K17/00; H03K19/003; H03K19/0185; H03K19/0944; H03M11/02; (IPC1-7): B01D59/00; F22B3/00