PURPOSE: To eliminate the need for controlling a program for an FIFO register by providing a writing data pointer and a reading data pointer as hardware components and controlling both pointers in order to use prescribed addresses in a data memory as the FIFO register.

CONSTITUTION: Respective address data respectively outputted from the writing data pointer 4 and the reading data pointer 5 are sequentially compared with each other by a comparing means 8 and a control circuit 10 is controlled by the output of the comparing means 8. The operation of the pointer 4 and that of the pointer 5 are alternately controlled by the output of the control circuit 10. Thereby, the writing operation and reading operation of the FIFO register 2a are alternately executed. Consequently, the FIFO register 2a using the prescribed addresses of the data memory can be surely driven without generating a trouble.