Title:
ADAPTIVE FILTER
Document Type and Number:
Japanese Patent JP3222646
Kind Code:
B2
Abstract:
PURPOSE: To reduce the manufacture cost by providing a means allowing a learning signal generating means to generate a specific signal so as to reduce the circuit scale.
CONSTITUTION: Signals whose frequencies are f0+f1 and f0-f1 appear at an output terminal of a multiplier 12 receiving signals whose frequencies are f0, f1, generated from frequency generating circuits 10,11. An output terminal of an adder 13 provides an output of an output signal from the multiplier 12 (signals whose frequencies are f0+f1, f0-f1) and a sum signal 2A whose frequency is f0. Then an inverter 14 shifts the phase of the signals whose frequencies are f0+f1 and f0-f1 by 180° and an attenuator 15 attenuates an output signal level of the inverter 14. Then an output terminal of an adder 16 outputs ideal output signals 6A whose frequencies are f0, f0+f1 and f0-f1. However, since the frequency components f0+f1 and f0-f1 are attenuated by the attenuator 15, the level of the signal 6A is lower than the frequency component f0 by a predetermined quantity.
Inventors:
Toshio Adachi
Application Number:
JP19731993A
Publication Date:
October 29, 2001
Filing Date:
August 09, 1993
Export Citation:
Assignee:
Asahi Kasei Microsystem Co., Ltd.
International Classes:
H03H21/00; (IPC1-7): H03H21/00
Domestic Patent References:
| JP63149949A | ||||
| JP62231527A |
Attorney, Agent or Firm:
Yoshikazu Tani (1 person outside)