To make a microprocessor accessible to memory without taking a time without providing an address bus for memory and an address bus for an I/O differently.

In the address bus device which is provided with a memory 1, an I/O device 2, a microprocessor 3 which accesses either of accessed parts 10 that are the memory 1 and the device 2 in accordance with a selection signal and an address bus 6 which transmits an active signal that makes the parts 10 having an access destination active and a designation signal that designates the access destination in the accessed parts, the bus 6 simultaneously transmits the active signal and the designation signal.