PURPOSE: To reduce the scale of a floating point arithmetic circuit containing an addition/subtraction circuit and a multiplication/division circuit, by using a normalizing circuit of the addition/subtraction circuit when the normalizing process is carried out for multiplication and division.
CONSTITUTION: In a circuit 204, high-order 1-bit and zero are added to an exponent part 134 when this part 134 to be normalized is supplied for the normalizing process of multiplication/division. Then the shift number '135' for normalization is subtracted from the part 134 of 8 bits. Thus the normalized 8 bits of the exponent part are obtained and set to a register 115 or 125 which holds the exponent part of a multiplication/division circuit. Thus just a single bit is added to a path used to set said 8 bits to the register 115 and 125 from a register 137. In addition, a small logical change is possible with the circuit 204 since just a single bit is added to the arithmetic. While the mantissa part of multiplication/division undergoes the multiplication and division through a circuit 164 and is set to a register 165.
OMODA KOICHIRO
TANAKA TERUO
