PURPOSE: To speed up the normalization of floating point multiplication without adding any specific mechanism by forming a means for decoding 2 bits of a multiplied result in a normalizing floating point arithmetic system and controlling whether a mantissa part is to be shifted by one bit in an MSB direction or not and a means for modifying an exponential part on the basis of a decoded signal.

CONSTITUTION: The titled circuit can be applied to an arithmetic unit constituted so that the product sum arithmetic of data expressed as complements can be processed by 8 bits in the exponential part and 16 bits in the mantissa part through a pipe line. The arithmetic unit has an exponential part adder 1, a mantissa part arithmetic circuit 2, a zero detecting circuit 3 for a multiplier and a multiplicand, a decoder 4 for upper 2 bits of a multiplied result, a shifter circuit 5 for shifting the output of the mantissa part by one bit in the upper direction, a multiplexer 6 for selecting a shifted value, a non-shifted value or a constant in accordance with the output of the decoder 4, and a multiplexer 7 for substituting the output of an exponential part operating circuit by a constant. An accumulator unit part is constituted of an computing element 8 for executing the digit adjustment operation of the exponential part, a shifter circuit 9 for digit adjustment, an adder/subtractor unit 10, a normalizing circuit 11, and an accumulator register 12.