PURPOSE: To eliminate a processing by means of software, data transfer time and arithmetic processing time with an external computing element and to speed up processing rate by inputting data which is read from a storage element to CPU in an arithmeticprocessed state.

CONSTITUTION: When a read request is given from CPU 10 to DRAM 11, a chip selection signal is outputted from CPU 10 to an interruption detection part 21, and the address of a memory area indicated by the chip selection signal is transmitted to an address latch circuit 15. The interruption detection part 21 selects a mode corresponding to the type of interruption and transmits a mode signal when it is interrupted by CPU 10. A control timing generation part 22 starts an operation by a start trigger signal and changes the value of a counter in synchronizing with a system clock with a start address as an initial value. Consequently, various control signals are generated in a generated timing pattern. An address switching part 16 reads data from the designated address.