PURPOSE: To provide a dual port memory circuit suitable for inter-processor communication dealing with massive data by using a random access memory and giving priority over one access as against memory access signals from two CPU by means of a mediation circuit.

CONSTITUTION: A data bus connected to the data terminal DATA of SRAM 1 is connected to the data bus of a first port-side through a data bus input circuit 4 and an output circuit 5, and is connected to the data bus of a second port-side through an input circuit 6 and an output circuit 7. Address bus input circuits 2 and 3 and data bus input circuits 4 add 6 are constituted by three states buffers. The buses are connection-controlled by an access control signal inputted to an output enable terminal OE, and the access control signal is generated by the mediation circuit. The data bus output circuits 5 and 7 are constituted by the latch circuits of eight bits, and eight-bit data of SRAM 1 is fetched by a strobe signal which the mediation circuit generates.