Title:
ARITHMETIC UNIT USING VARIANCE ARITHMETIC
Document Type and Number:
Japanese Patent JP2633165
Kind Code:
B2
Abstract:
PURPOSE: To provide an arithmetic unit for product sum calculation which is fast in operation speed and can operate practically even when a high frequency is used and has a constitution of its input stage made simpler.
CONSTITUTION: This unit is equipped with BOL as a latch part which is connected to an input end and composed of a parallel bit Input/serial two-bit output type latch, address registers(AR) 10 and 11 which are connected to the output side of BOL and drive ROM addresses, ROMs 20 and 21 which are connected in series with ARs 10 and 11 and store previously calculated values, a 1st adder 30 which is connected to the output sides of the ROMS 20 and 21 and adds the outputs of the ROMs 20 and 21, a pipeline register(PR) 40 which is connected to the output side of the 1st adder, a 2nd adder 50 which has its one input side connected to the output side of the PR 40, and a shift register(SR) 60 which stores the output of the 2nd adder 50, and shifts it to the right by two bits and feeds it back to the other input side of the 2nd adder 50; and arithmetic data are processed by two bits at each time.
Inventors:
KIN SANSHOKU
Application Number:
JP255793A
Publication Date:
July 23, 1997
Filing Date:
January 11, 1993
Export Citation:
Assignee:
SANSEI DENSHI KK
International Classes:
G06F17/10; G06F7/38; G06F17/16; (IPC1-7): G06F17/10; G06F17/16
Domestic Patent References:
| JP247769A | ||||
| JP3149656A | ||||
| JP1189765A |
Other References:
ＩＥＥＥ ＴＲＡＮＳＡＣＴＩＯＮ ＯＮ ＣＩＲＣＵＩＴＳ ＡＮＤ ＳＹＳＴＥＭＳ，ＶＯＬ．３６，ＮＯ．４（１９８９−４）Ｐ．６１０−６１７
Attorney, Agent or Firm:
Takeshi Takatsuki
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