Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
AUTOMATIC EQUALIZER, SAMPLING CLOCK GENERATING METHOD USED FOR THE SAME AND RECORDING MEDIUM
Document Type and Number:
Japanese Patent JPH11225174
Kind Code:
A
Abstract:

To provide an automatic equalizer that selects an optimum sample timing by taking into account the effects of a demodulation component, a pre- cursor component and a post-cursor component and the like.

An automatic equalizer consists of a sampler 101, a substructure 102, an impulse response arithmetic circuit 103, a discrimination device 109, a sampling clock output circuit 111, and a reception signal estimate circuit 112. The sampling clock output circuit 111 determines as optimum sample timing where characteristic deterioration due to a pre-cursor component is small and characteristic enhancement by a post-cursor is high by taking into account a demodulation component, the pre-cursor component and the post-cursor component or the like. Thus, the sample timing is selected more optimally by taking the effect other than a peak value of impulse response into account.


Inventors:
SHIKAKURA GIICHI
OSAWA TOMOYOSHI
Application Number:
JP2247598A
Publication Date:
August 17, 1999
Filing Date:
February 04, 1998
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
H03H15/00; H04B3/06; H04B3/14; H04L7/02; H04L25/03; H04L25/40; (IPC1-7): H04L25/03; H03H15/00; H04B3/14; H04L25/40
Attorney, Agent or Firm:
Yanagi Kawa Shin