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Patent Searching and Data


Title:
BIT ERROR REDUCTION SYSTEM
Document Type and Number:
Japanese Patent JPH04290316
Kind Code:
A
Abstract:

PURPOSE: To reduce bit errors without deteriorating transmission efficiency at the time of block transfer through radio lines.

CONSTITUTION: In digital data communication system equipped with 'a transmission part 11 encoding transmission data using an error correction code and performing transmission to the radio line through demodulation system performing the multi-value transfer with frame construction including the synchronizing code in consecutive prescribed number of bit units and a reception part 13 obtaining the reception data while performing frame synchronization and decoding to demodulated bit lines, an interleave processing means 15 exchanging bit arrangement to the consecutive bit units of the transfer unit of the multi-value transfer in the block and supplying demodulated demodulation signal is provided on the transmission part 11 and a deinterleave processing means 17 obtaining data to be processed by extracting the interleave block from the demodulated bit lines and recovering bit arrangement is provided in the reception part 13.


Inventors:
YAMASHITA ATSUSHI
Application Number:
JP5487991A
Publication Date:
October 14, 1992
Filing Date:
March 19, 1991
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L1/00; H03M13/27; (IPC1-7): H03M13/22; H04L1/00
Attorney, Agent or Firm:
Furuya Fumio