To shorten an access time and to perform high speed operation without requiring a new circuit.

This device has a 3 bits binary counter a1 to which initial addresses A0, A1, A2 are loaded by an initial address load signal 1d and which is operated synchronizing with clock signals (CK, /CK) composing of continuous pulse train, a 2 bit binary counter a2 which is initialized by a reset signal and operated synchronizing with clock signals (CK, /CK) composing of continuous pulse train, and a carry signal selecting circuit a3 selecting carry signals (crya0, crya1) being carry signals from the 3 bits binary counter a1 or carry signals (cryb0, cryb1) being carry signals from the 2 bits binary counter a2 by a burst mode switching signal.