To improve write-in speed and to shorten a time required for erasure.

A memory cell which makes contents address possible comprises a first memory transistor Q1 and a first select-transistor S1 cascade-connected between a word line WL and a match line ML, and a second memory transistor Q2 and a second select-transistor S2. Gates of the first and the second memory transistors Q1, Q2 are connected to a control gate line CG, a gate of the first select-transistor S1 is connected to a first bit line BL1, a gate of the second select-transistor S2 is connected to a second bit line BL2. As the device has the select-transistors S1, S2, source side injection write-in can be performed, also, even if over-erasure is performed, as an off-leak current can be prevented, the number of times of applying erasure pulses can be decreased.