Title:
BUS DRIVER
Document Type and Number:
Japanese Patent JP2590758
Kind Code:
B2
Abstract:
PURPOSE: To reduce the unnecessary signal output produced from a 1st buffer circuit and to operate a bus driver with a small power consumption by adding a capacitive part to the output part of the 1st buffer circuit.
CONSTITUTION: The output part of a 1st buffer circuit 1 is connected to one of both terminals of a capacitive parts 2, and the output part of a delay circuit 3 is connected to the input part of a 2nd buffer circuit 4. The other terminal of the parts 2 and the output part of the circuit 4 are connected to a signal output terminal 6. An ordinary tri-state circuit or open collector circuit will do for the circuits 1 and 4, and the MOS or Pn capacity consisting of a memory cell, etc., is available for the parts 2. Thus, it is possible to control the amount of current received from the circuit 1 for reduction of the power consumption and also to properly control the signal waveform by adding the parts 2 to the output part of the circuit 1.
Inventors:
KAMYA HIROSHI
Application Number:
JP26701394A
Publication Date:
March 12, 1997
Filing Date:
October 31, 1994
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F3/00; H03K4/00; H03K6/04; H03K17/16; H03K19/0175; (IPC1-7): G06F3/00; H03K19/0175
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)