PURPOSE: To reduce power consumption by differentiating the channel types of source followers of the initial and second stages, and setting a through-current flowing through the follower of the second stage at CCD output resetting time.

CONSTITUTION: When a reset clock R comes to 'H' level, NFD is reset to VR level through a reset gate 3. The output voltage of the follower of the first stage at this time is represented by V'R. If VDD2 is set to a potential lower than the V'R, since a DOUT terminal cannot become a potential higher than the VDD2, a transistor 12 is turned OFF, and currents to flow through transistors 11, 22 do not flow in this state. If the clock R comes to 'L' level, the potential of NFD becomes VR-VFT due to the capacitive coupling between the gate 3 and the NFD. When the threshold voltage of the transistor 11 is represented by VTH and VR-VFT+VTH<VDD2 is satisfied, the transistor 11 which was turned OFF becomes ON to start operating as a normal source follower.