PURPOSE: To raise a critical OFF voltage rising rate at commutation time by providing the steps of forming one conductive type emitter region in a base region and specifying a heat cooling speed in diffusing step to induce a thermal crystal defect due to a thermal distortion, thereby reducing a gate input signal current.

CONSTITUTION: A P-type insulating layer 12 is formed in an N-type silicon substrate 11 as a triac element, and P-type base regins 13, 14 are formed. Here, a diffusion is performed so that the mean electric conductivity σ of the layer 13 falls in a range of 2.5∼5(Ω.cm)-1. Then, N-type emitter regions 15, 16, 17 are formed by diffusing. At this time, the differences xjt between the depth xjN of the regions 13, 14 and the depth xjN of the regions 15, 16, 17 are con trolled to fall in a range of 15∼25μm so that the value of σ×xjt becomes 5∼10×10-3Ω-1. When the silicon substrate is cooled in the final diffusing step, it is performed under the conditions of 20∼80°C/min to apply a thermal distor tion to the substrate, thereby reducing an electron lifetime.