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Title:
CIRCUIT FOR DOUBLING RESOLUTION OF PROGRAMMABLE FREQUENCY DIVIDER
Document Type and Number:
Japanese Patent JPH1093427
Kind Code:
A
Abstract:

To double the resolution without raising the frequency of an original oscillation signal by providing an inversion/noninversion control circuit inverting/ noninverting the original oscillation signal and a selection means validating/ invalidating the signal for a programmable frequency divider.

The inversion/noninversion control circuit 1 is arranged in the middle of the original oscillation signal line inputting to a programmable counter 10 to connect an inversion/noninversion selective signal P0 and the counter signal of the inversion/noninversion control circuit. This circuit 1 consists of an OR circuit and an exclusive OR circuit and inputs the output of a frequency halving divider 11 through a delay circuit 30 in order to stabilize the counter signal I of the inversion/noninversion control circuit. In addition the signal P0 indicates the changing timing of the programmable frequency divider 11 to the original oscillation signal and outputs a signal validating/ invalidating the circuit 1. Thereby resolution is doubled without raising the frequency of the original oscillation signal.


Inventors:
ASANUMA TOSHIYA
Application Number:
JP26509396A
Publication Date:
April 10, 1998
Filing Date:
September 17, 1996
Export Citation:
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Assignee:
SIGMA CORP
International Classes:
H03K21/00; H03K23/64; (IPC1-7): H03K23/64; H03K21/00