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Patent Searching and Data


Title:
CIRCUIT AND METHOD FOR PROGRAM VERIFICATION
Document Type and Number:
Japanese Patent JPH11317085
Kind Code:
A
Abstract:

To provide a program verifying circuit which is assembled in a memory cell, that stores multivalued data and is electrically reloadable, has a simple circuit constitution and causes no increase in the layout area.

The program verifying circuit is constituted of a variable threshold voltage field effect transistor TRn having plural input gate electrodes 47A and 47B and a latch circuit 20. The circuit 20 is connected to one of the source/ drain regions of the transistor TRn and also connected to a memory cell through a bit line BT. One of the electrodes of the transistor TRn, i.e., the electrode 47A is connected to the memory cell through the line BT. A potential is applied to the other electrode 47B, to control the connection/disconnection of the transistor TRn.


Inventors:
SUGIYAMA HISANOBU
Application Number:
JP12582098A
Publication Date:
November 16, 1999
Filing Date:
May 08, 1998
Export Citation:
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Assignee:
SONY CORP
International Classes:
G11C11/56; G11C16/02; G11C16/34; (IPC1-7): G11C16/02
Attorney, Agent or Firm:
Takahisa Yamamoto