Title:
CIRCUIT AND METHOD FOR SHAPING INTEGRATED WAVEFORM
Document Type and Number:
Japanese Patent JP3515798
Kind Code:
B2
Abstract:
PURPOSE: To improve the stability of a waveform shaping circuit by forming the shaping circuit by integrating the functionality of an addition resistance network and a filter in a single integrated circuit together with a transmission stage to suppress the radiation of a higher harmonic component and, at the same time, reducing the occupying area of the circuit.
CONSTITUTION: In a waveform shaping circuit 10, an input logic stage 14 and a delay input logic stage 16 generate a plurality of pairs of logic and delayed logic signals in response to a plurality of incrementally delayed timing signals TS1-TSn generated from a phase locked loop 12 in accordance with OSC signals. In response to these signals, a weighted current adding stage 18 generates output data signals and complementary output data signals and finds an instantaneous value by summing the incremental parts of the signals. In addition, a waveform shaping circuit is formed by integrating these circuits in one integrated circuit. Therefore, the waveform shaping circuit can reduce unnecessary radiation of a higher harmonic component as a single integrated circuit by obtaining a pair of complementary sine output waves without using any external waveform shaping component by transforming input data signals and delayed input data signals and, at the same time, the stability of the circuit can be improved by reducing the occupying area of the circuit and an unstable element, such as the temperature fluctuation, etc.
Inventors:
Segaram, Para K.
Application Number:
JP32373593A
Publication Date:
April 05, 2004
Filing Date:
December 22, 1993
Export Citation:
Assignee:
NATL SEMICONDUCTOR CORP <NS>
International Classes:
H03M5/12; H03M1/74; H04L25/02; H04L25/03; H04L25/04; (IPC1-7): H04L25/02; H03M5/12; H04L25/03
Attorney, Agent or Firm:
古谷 馨 （外２名）