Title:
CIRCUIT AND METHOD FOR SIGNAL PROCESSING
Document Type and Number:
Japanese Patent JP3485088
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a signal processing circuit and a signal processing method which can perform signal processing of a pulse signal at an accurate cycle.
SOLUTION: This signal processing circuit 30 provided in a wobble signal processing part 48, consists of a positive polarity gate 71, a negative polarity gate 72, a counter circuit (positive polarity) 73, a counter circuit (negative polarity) 74, latch circuits 75 and 76, a switching circuit 78, a digital LPF 79, an R-S flip-flop 77, delay circuits 80, 81 and 82 and an OR gate 83. It is possible to eliminate chattering and to perform signal processing at a more accurate cycle by providing the signal processing circuit with the two positive and negative polarity gates in this way.
Inventors:
Akira Mashita
Keiji Ueno
Keiji Ueno
Application Number:
JP2000381245A
Publication Date:
January 13, 2004
Filing Date:
December 15, 2000
Export Citation:
Assignee:
TEAC Corporation
International Classes:
G11B20/14; H03D3/00; H03D3/04; H04L25/34; G06F1/06; (IPC1-7): G11B20/14; H03D3/00
Domestic Patent References:
| JP8214033A |
Attorney, Agent or Firm:
Tadahiko Ito
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