Title:
INPUT/OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JP3429455
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent all transistors(TRs) inside an LSI from being destroyed.
SOLUTION: This input/output circuit consists of a bonding pad 2 that is connected to a high voltage signal line at the outside of an LSI internal power supply voltage, high level output circuit sections 29, 31 consisting of a floating n-well system P-channel TRs and an analog switch and outputting an LSI internal signal to an external device, low level output circuit sections 30, 32 consisting of series connection of a plurality of N channel TRs and outputting the LSI internal signal to an external device, and an internal control circuit section 48 that provides a difference to a conduction time of the high level output circuit sections 29, 31 and the low level output circuit sections 30, 32. The internal control circuit section 48 generates a control signal to control the high level output circuit sections 29, 31 and the low level output circuit sections 30, 32.
Inventors:
Masanori Hirofuji
Application Number:
JP8591199A
Publication Date:
July 22, 2003
Filing Date:
March 29, 1999
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L21/8238; H01L27/092; H03K17/08; H03K17/16; H03K17/687; H03K19/0175; (IPC1-7): H03K19/0175
Domestic Patent References:
| JP9238065A | ||||
| JP10233674A | ||||
| JP3189994A | ||||
| JP8228141A |
Attorney, Agent or Firm:
Akio Miyai