Title:
プログラマブルロジックデバイス回路に結合されるクロックデータリカバリ回路
Document Type and Number:
Japanese Patent JP5237985
Kind Code:
B2
Abstract:
A programmable logic device ('PLD') is augmented with programmable clock data recover ('CDR') circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling ('LVDS'). The circuitry may be part of a larger system.
Inventors:
Edward Aun
Louis Henry
Paul Butler
John Turner
Rakesh patel
Jeong Li
Louis Henry
Paul Butler
John Turner
Rakesh patel
Jeong Li
Application Number:
JP2010101545A
Publication Date:
July 17, 2013
Filing Date:
April 26, 2010
Export Citation:
Assignee:
Altera Corporation
International Classes:
H04L7/033; H04L7/04; G11C7/22; H03K19/177; H03L7/07; H03L7/08; H03L7/081; H03L7/099; H03L7/187; H03M9/00; H04L7/02; H03L7/089; H03L7/199
Domestic Patent References:
| JP10134523A | ||||
| JP4274542A | ||||
| JP9149017A | ||||
| JP63121344A | ||||
| JP7058731A | ||||
| JP6327072A | ||||
| JP11317731A | ||||
| JP11317730A | ||||
| JP63108238U | ||||
| JP6048243U | ||||
| JP4199912A |
Foreign References:
| US6031428 |
Other References:
Jason Konstas,Converting Wide, Parellel Data buses to High Speed Serial links,International IC '99 Conference Proceedings,米国,p.19-30,1999年
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita
Takaaki Yasumura
Natsuki Morishita