To provide a clock generating apparatus for warranting an operation response when a frequency of an output signal is unstable in an operation start state or the like and reducing the power consumption.
A PLL circuit 1 is provided with: a VCO 2; a feedback signal generating circuit 3 for generating a feedback signal PLL_FB resulting from applying 1/N frequency division to the frequency of the output signal PLL_OUT; a phase comparator circuit 4; a charge pump circuit 5; and an LPF 6. The feedback signal generating circuit 3 is provided with: a first frequency divider circuit 21 with a high maximum operating frequency; a second frequency divider circuit 22 with a low maximum operating frequency; a convergence detection circuit 13 for detecting whether or not the frequency of the output signal PLL_OUT converges on a target value, and a switching circuit 15. The switching circuit 15 selects the first frequency divider circuit 21 to allow the circuit 21 to carry out frequency division processing when the frequency of the output signal PLL_OUT does not converge on the target value, and the switching circuit 15 selects the second frequency divider circuit 22 to allow the circuit 22 to carry out frequency division processing when the frequency of the output signal PLL_OUT converge on the target value.
| JPH11219157 | SAMPLING CLOCK CONTROL DEVICE |
| JPH08235789 | PLL CIRCUIT |
| JPH09233501 | IMAGE PROCESSOR |
HARADA SHINGO
HIGUCHI NAOHIRO
Eiichi Tamura
Seiji Iga
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