To provide the clock signal generating circuit that easily generates clock signals with a plurality of frequencies without increasing the cost and making the circuit remarkably complicated and large-sized based on a signal oscillated by one kind of frequency.
The circuit is provided with an oscillator 2 that outputs a signal with a prescribed frequency, a variable counter 4 that executes count synchronously with an original oscillation clock 2a outputted from the oscillator 2 and provides an output of a carry signal 4a when the count reaches a count designated by a load value signal 5a, a load value change timing generating section 3 that designates sequentially a new count to the variable counter 4 when the carry signal 4a is outputted by number of times corresponding to the designated count, and a load value control section 5.
JP4977774 | Data processing device |
JPH052436 | VERY HIGH SPEED LOGIC CIRCUIT |