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Title:
CLOCK GENERATING CIRCUIT AND CLOCK GENERATING METHOD
Document Type and Number:
Japanese Patent JPH11186899
Kind Code:
A
Abstract:

To provide the clock signal generating circuit that easily generates clock signals with a plurality of frequencies without increasing the cost and making the circuit remarkably complicated and large-sized based on a signal oscillated by one kind of frequency.

The circuit is provided with an oscillator 2 that outputs a signal with a prescribed frequency, a variable counter 4 that executes count synchronously with an original oscillation clock 2a outputted from the oscillator 2 and provides an output of a carry signal 4a when the count reaches a count designated by a load value signal 5a, a load value change timing generating section 3 that designates sequentially a new count to the variable counter 4 when the carry signal 4a is outputted by number of times corresponding to the designated count, and a load value control section 5.


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Inventors:
KAN HIYOU
Application Number:
JP35581997A
Publication Date:
July 09, 1999
Filing Date:
December 24, 1997
Export Citation:
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Assignee:
ANDO ELECTRIC
International Classes:
G06F1/04; H03K21/00; H03K23/64; (IPC1-7): H03K21/00; G06F1/04; H03K23/64
Attorney, Agent or Firm:
Hiroshi Arafune (1 person outside)



 
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