To provide a clock signal generating circuit that generates a clock signal with a frequency division ratio expressed in an optional fraction from an original oscillation frequency.

A master clock signal IN is counted by a count section 20, and a selection signal SEL goes to 'H' when the count CNT1 is 0 to 3. Thus, the master clock signal IN is frequency-divided into 1/4 by a counter 21 and an OR 22. On the other hand, when the count CNT1 is 4 to 9, the selection signal SEL goes to 'L', and the master clock signal IN is frequency-divided into 1/3 by a counter 24, an AND 25 and an OR 26. An OR 27 provides an output of three pulses with respect to 10 pulses of the master clock signal IN, and then a clock signal CLK frequency-divided into an arbitrary fraction (e.g. 3/10) is obtained.