To provide a circuit for generating a clock with frequencies stable against the fluctuation of a surrounding temperature or the fluctuation of a power supply voltage being the factor of the fluctuation of frequencies.

At the time of initialization, the frequency division rate data of a frequency-divider 330 are fetched from a CPU 400 in a data register 340 so that a clock signal can be outputted from the frequency-divider 330. Afterwards, the frequencies of an original clock signal PCLKA from a first oscillator 310 are compared with the frequencies of an original clock signal PCLKB from a second oscillator 320 in a prescribed interval, and the count value of an addition/subtraction counter 360 is added/subtracted according to the compared result, and the added/subtracted count value is re-fetched in the data register 340.