Title:
CLOCK GENERATION CIRCUIT FOR DIGITAL VIDEO PROCESSOR
Document Type and Number:
Japanese Patent JP3304036
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a circuit capable of performing a stable operation in the processing systems of both luminance signals and chrominance signals by simple constitution in a digital video processor by providing the respective means of burst phase error detection, oscillation and frequency division.
SOLUTION: Inputted composite video signals are clamped by a clamp circuit 1 and further, digitized by an A/D converter 2. Digital luminance signals and digital chrominance signals are separated from the digitized composite video signals by a Y/C separation circuit 3. The digital chrominance signals are turned to R-Y signals by being multiplied with color sub carrier wave signals from sine wave ROM 17 in a multiplier 5 and then being passed through an LPF 7. They are turned to B-Y signals by being multiplied with the color sub carrier wave signals whose phase is shifted for 90 degrees from the sine wave ROM 17 in the multiplier 6 and then being passed through the LPF 8. Corresponding to the R-Y signals and the B-Y siqnals, color burst phase error signals are detected in a burst phase detection part 9.
Inventors:
Toru Senbongi
Matsunaga et al.
Hiroshi Odanaga
Matsunaga et al.
Hiroshi Odanaga
Application Number:
JP10038796A
Publication Date:
July 22, 2002
Filing Date:
April 22, 1996
Export Citation:
Assignee:
Motorola, Inc.
International Classes:
H04N9/45; H04N9/44; (IPC1-7): H04N9/44; H04N9/45
Domestic Patent References:
| JP63261976A | ||||
| JP879781A | ||||
| JP2113792A |
Attorney, Agent or Firm:
Yoshiaki Ikeuchi