Title:
クロック生成回路のテスト回路
Document Type and Number:
Japanese Patent JP4819400
Kind Code:
B2
Abstract:
A testing circuit measures a center frequency of a clock signal outputted by a clock generator. The clock generator has a frequency modulator capable of (1) performing a frequency sampling accurately for the duration of modulation frequency and reducing the duration for frequency measurements, and (2) implementing proper testing of the down-spread controlling feature as one of the SSCG modulation functions by accurately determining the center frequency of the clock signal. The testing circuit measures a center frequency of a clock signal outputted by a clock generator by converting an analog modulation signal into a digital signal and outputting the digital signal, counting the period of the clock signal to obtain a count according to the digital signal outputted by the clock generator, and comparing the count with the predetermined specification values related to the center frequency of the clock signal to obtain and output a comparison result.
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Inventors:
Yuji Watanabe
Application Number:
JP2005154310A
Publication Date:
November 24, 2011
Filing Date:
May 26, 2005
Export Citation:
Assignee:
株式会社リコー
International Classes:
H03K5/19; G01R31/28; G06F1/04; H01L21/822; H01L27/04; H03K4/06; H03L7/095; H03M1/34; H04L7/033
Domestic Patent References:
| JP63187949A | ||||
| JP2002305446A | ||||
| JP2004207846A |
Other References:
山中英夫著,「パルス計測の基礎と応用」,日本,株式会社産報,1972年11月10日,初版,初版,レシプロカル方式のカウンタ
Attorney, Agent or Firm:
Mitsuo Tanaka
Kyousei Tamura
Masahiro Ishino
Kyousei Tamura
Masahiro Ishino