Title:
CLOCK SYNCHRONIZED TYPE SEMICONDUCTOR MEMORY DEVICE AND ACCESS METHOD THEREOF
Document Type and Number:
Japanese Patent JP2740097
Kind Code:
B2
Abstract:
PURPOSE: To deal with a high speed and frequent column address by storing data in a serial register by the order of data determined in accordance with the column address.
CONSTITUTION: The assignment of a block that is set in the state of access operation is performed by the prescribed bit of the address data; and the exchange of data with the register and the outside is performed by output and input buffers 5, 6. Then, when the leading address for the start of the data access is given in a scrambler control circuit 1, the selection order for the scrambler circuits 2a-2d is set in a prescribed order. Here, a memory cell part is divided into two blocks A, B, and when one starts the access operation, the other becomes the state of access standby. Then, in accordance with the column address given at the time of storing the data in the output serial register 3 from the blocks A, B, the storing is performed by the order of the data. Consequently, while the order of access is always kept fixed, the high speed and frequent change in the column address is dealt with.
Inventors:
Haruki Toda
Yuko Watanabe
Hisayama Hitoshi
Shozo Saito
Yuko Watanabe
Hisayama Hitoshi
Shozo Saito
Application Number:
JP34190792A
Publication Date:
April 15, 1998
Filing Date:
December 22, 1992
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C11/407; G11C7/22; G11C8/18; G11C11/401; G11C11/41; H01L27/10; (IPC1-7): G11C11/407; G11C11/401; G11C11/41; H01L27/10
Domestic Patent References:
| JP660640A | ||||
| JP3113795A | ||||
| JP60117786A |
Other References:
日経エレクトロニクス （１９９２−５−１１） Ｐ．１４３−１４７
Attorney, Agent or Firm:
Takehiko Suzue