PURPOSE: To prevent fluctuation of a duty factor due to a circuit element and to facilitate the initial design of the circuit by limiting the element causing fluctuation of the duty factor.

CONSTITUTION: A frame signal including a frame synchronizing pulse FP, a serial data signal DATA whose '1' and '0' are represented respectively by a high level and a low level and a clock signal CLK whose duty ratio is 50% are inputted to a CMI coding circuit, and an output signal (13) of the CMI code is generated from a NAND circuit 34. Then the leading and trailing edges of the output signal (13) is decided by the trailing edge of signals (10)-(12) and the trailing edge of the signals (10), (12) depends on the operating characteristic of NAND circuits 30, 31 and an OR circuit 32 and the input clock only. Since the element causing fluctuation of the duty ratio is limited in this way, a coded output holding the duty of the input clock is generated and the design and manufacture of the circuit are facilitated.