Title:
COINCIDENCE DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JP2768287
Kind Code:
B2
Abstract:
PURPOSE: To provide a coincidence detection circuit in which coincidence is detected with a simple circuit while relieving the load on a CPU and allowing the CPU itself to discriminate propriety of input data.
CONSTITUTION: A shift register 20 shifts serial data SD from an input terminal 11 based on a clock CLK from an input terminal 12. A coioncidence discrimination circuit 30 starts discrimination of coincidence between the input serial data SD from the input terminal 11 with data SFDn-1 shifted by n-stages from the shift register 20 to provide an output of a coincidence discrimination bit DET. A latch circuit 40 latches output data SFD0-SFDn-1 of the shift register 20 and the discrimination bit DET synchronously with the latch timing from the input terminal 14 to provide an output of output data PD0-PDn-1 to output terminals 510-51n-1 and the discrimination bit DET to an output terminal 52.
Inventors:
Ueno Tsukasa
Application Number:
JP398095A
Publication Date:
June 25, 1998
Filing Date:
January 13, 1995
Export Citation:
Assignee:
NEC
International Classes:
H03M9/00; G06F7/02; H04L1/08; H04L7/00; (IPC1-7): H04L1/08
Domestic Patent References:
| JP63202148A |
Attorney, Agent or Firm:
Matsuura
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