PURPOSE: To send data at a maximum transmission period independently of frequency dividing ratios by arranging sequentially data in serial bit incoming in real time from the parallel bit location corresponding to the head at parallel serial conversion.

CONSTITUTION: An address counter 24 is initialized by a control signal CLR at the head of a basic transmission period, a head bit of the serial data this time is written on Q0 of a serial/parallel converter 23 by the inverse of ENA signal. In case of 1/2 frequency division, when the serial data in the basic transmission period comes, data a0∼a3 of 4 bits are written sequentially from the Q0 to the Q3 of the serial/parallel converter 23 and sent. In case of 1/4 frequency division, the transmission quantity at the basic transmission period is 2 bits and in case of 1/8 frequency division, the transmission quantity at the basic transmission period is 1 bit and the data is written sequentially from the Q0 of the converter 23 respectively, then the time of the head bit sent from a parallel/serial converter 22 is the same as the case with the basic transmission speed.