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Title:
COMPLEMENTARY MOS CIRCUIT
Document Type and Number:
Japanese Patent JPS5549037
Kind Code:
A
Abstract:

PURPOSE: To obtain a circuit which oscillates easily with low power consumption by connecting P and N-channel MOSFETs and C-MOSFET together in series between power terminals, by connecting a resistance in parallel to C-MOS and by providing a gate with a control input terminal.

CONSTITUTION: Between power supplies VDD and VSS, P-MOSFETs T11 and T13 and N-MOSFETs T12 and T14 are connected and resistances RDD and RSS are also connected to T13 and T14 in parallel. From a connection point of T13 and T14, input signal XT is supplied and from resistances RDD and RSS, output signal -XT is extracted. Between gates of T13 and T14, inverter In is connected and from the gate of T14, control signal is supplied. At an oscillation start, signal SW is held at a "H" level and T13 and T14 are both made conductive to decrease effectively a resistance between T11 and T12 and an oscillation start voltage is made higher than a power voltage across a lithium battery, thereby simplifying oscillation. In stationary operation, signal SW is held at a "L" level and T13 and T14 is cut off to suppress power consumption by using resistances RDD and RSS.


Inventors:
YOSHITAKE KAZUKI
ANDOU TAKESHI
Application Number:
JP12325278A
Publication Date:
April 08, 1980
Filing Date:
October 05, 1978
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03K19/0948; H03K19/00; (IPC1-7): H03K19/094
Domestic Patent References:
JPS5229144A1977-03-04



 
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