Title:
ANALOG/DIGITAL CONVERTER FOR MULTI-BIT SIGMA DATA OF DIGITAL COMPENSATION TYPE
Document Type and Number:
Japanese Patent JP3318219
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce power consumption and to reduce the size of a hardware by using a recycle analog/digital converter and executing digital correction and compensation for error data.
SOLUTION: A flash analog/digital converter 40 converts held signals to digital signals in response to clock signals Q1 and generates the digital signals of 4 bits. A digital correction means 44 inputs the 4-bit digital signals provided from the flash A/D converter 40, performs the digital correction and outputs the corrected digital signals of 16 bits. A digital compensation means 46 generates corresponding digital compensation signals in responses to the high- order 4-bit signals of the digital signals of 16 bits corrected in response to the clock signals Q1. An addition means 48 adds the signals of 16 bits for which the digital correction is performed and the digital compensation signals of 16 bits and generates the signals of 16 bits for which digital compensation is performed.
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Inventors:
Li Narihiro
Application Number:
JP33074896A
Publication Date:
August 26, 2002
Filing Date:
December 11, 1996
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H03M1/06; H03M1/12; H03M3/02; H03M3/04; (IPC1-7): H03M3/04; H03M1/06; H03M1/12
Domestic Patent References:
| JP6393225A | ||||
| JP1319330A | ||||
| JP376318A | ||||
| JP3218121A | ||||
| JP4207817A | ||||
| JP6244734A |
Attorney, Agent or Firm:
Hidekazu Miyoshi (1 outside)