To provide a test circuit and method in which an A/D converter mounted on a small-sized integrated circuit, which has neither a D/A converter nor a bulk memory, can be tested with small numbers of pins.

A maximum value detection circuit 2, a minimum value detection circuit 3 and a variance value computation circuit 5 are provided to which a series of digital data obtained by converting analog signals through an A/D converter 20 are input. Each of the circuits 2, 3, 5 is reset to a prescribed initial value before starting inputting the analog signal to the A/D converter 20. When data larger (smaller) than data held at a present time point are input during the input of a series of digital data, the circuit 2(3) updates the held data to input data and the circuit 5 performs variance computation to update the held data. After the input of a series of digital data is completed, the held data in the circuits 2, 3, 5 can be output to an external tester as a maximum value, a minimum value and a variance value of the digital data, respectively.