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Patent Searching and Data


Title:
FREQUENCY/VOLTAGE-CONVERTING CIRCUIT
Document Type and Number:
Japanese Patent JPH10145202
Kind Code:
A
Abstract:

To contrive high linearization of conversion, wide range and low noise by extracting a DC component from an output signal outputted from a phase comparator for phase-comparing an input signal and the output signal of an active delay circuit.

An active delay circuit 1 which is composed of a transistor and a resistance is provided as a circuit for delaying an input differential signal, and the phase comparator 2 is formed in excessive response restraining type. In this active delay circuit 1, if an input signal is entered in input terminals 4 and 4N, a signal delayed by a delay time Tbd of gate delay is outputted from output terminals 6 and 6N. Then, to an input signal inputted to the phase comparator 2 from the input terminals 4 and 4N, delay time fluctuation of the delayed input signal inputted from this active delay circuit 1 is restrained. That is, the phase comparator 2 phase-compares the input signal and the output signal of the active delay circuit 1. Then, a low-pass filter 4 extracts a DC component from the output signal outputted from the phase comparator 2.


Inventors:
KISHINE KEIJI
HIROSE MASAKI
ISHIHARA NOBORU
KISHIMOTO TOMOMASA
KIKUSHIMA KOJI
SAKURAI HISAYA
IKEDA SATOSHI
Application Number:
JP31686896A
Publication Date:
May 29, 1998
Filing Date:
November 14, 1996
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H03D3/06; H03D3/18; H03K9/06; (IPC1-7): H03K9/06; H03D3/06; H03D3/18
Attorney, Agent or Firm:
Nagao Tsuneaki