To provide a counter circuit that surely performs a self reset when a count proceeds, reaches a specified value or an overflow occurs and is capable of preventing a mis-operation, when a count operation is restarted.

This circuit is equipped with a counter BC1 for outputting a count signal A which shows the number of pulse of a clock , a counter BC2 for outputting a count signal B which shows the number of pulse of the count signal A, a counter BC3 for outputting a count signal C which shows the number of pulse of the count signal B, a counter reset detection circuit AGR1 101 which output a signal when counter signals A to C are given and an overflow occurs, a counter reset detection circuit AGR0 100 for outputting a signal when all the count signals A to C become a logic '0', and an RS flip-flop RS1 which gives a counter reset signal CRE to all the counters from the time when the circuit AGR1 101 outputs the signal to the time, when the circuit AGR0 100 outputs a signal and has them reset. It is possible to restart the count operation normally, after the resets of all the counters have been surely completed.