To provide a counter circuit that includes a test circuit, capable of quickly deciding whether or not a counter operation is normal.

When a counter operation starts, '1' is set with a counter operation signal at the time of normal operation, and a register 3 starts to input an output value of a selector 2 in a timing of, for example, a clock rising. The output value of a selector 2 of an input value of the register 3 is outputted to by an output value of an adder 1 of n-bit divided by the m-bit as the result of selection. At the same time, an output of a selector 6 outputs an output value of an adder 4 without the division, as the result of selection of the selector 6. The output value of the selector 2 and the output value of the selector 6 are inputted to an comparator 7 as a result of each addition operation and are compared. The operation result of the counter circuit is decided, depending on whether the comparison result is '0' or '1'.