Title:
COUNTER CIRCUIT
Document Type and Number:
Japanese Patent JP2994273
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce a packaging area, including a wiring part by ORing the output of a diode part for taking the wired OR connection of the opposite phase output of the specified stage and succeeding stages of flip-flops turned to multi-stage constitution and the opposite phase output of the flip-flop of an initial stage, inverting the output and feeding it back to an input gate part.
SOLUTION: An input gate circuit 1 synchronizes digital input D1-Dn and the flip-flops FF1-FFn of multiple stages supply the respective output of the input gate circuit 1, to set input S and supply a reference clock CLK to the synchronous input C of the initial stage and the positive phase output Q of a preceding stage to the synchronous input C of the second and succeeding stages. The diode part 2 takes the wired OR connection of the Q inverted output of the flip-flops FF2-FFn of the second and succeeding stages for not affecting an operating speed, and an OR gate 3 ORs the output B of the diode part 2 and the Q inverted output of the flip-flop FF1 of the initial stage. An inversion circuit 4 inverts the output A of the OR gate 3 and feeds it back to the input gate circuit 1.
Inventors:
Tomikawa Shoetsu
Application Number:
JP22909696A
Publication Date:
December 27, 1999
Filing Date:
August 29, 1996
Export Citation:
Assignee:
Yamagata NEC Corporation
International Classes:
H03K19/086; H03K23/00; (IPC1-7): H03K23/00; H03K19/086
Domestic Patent References:
| JP63283316A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
Previous Patent: POLYPHASE CLOCK GENERATING CIRCUIT
Next Patent: PORTABLE MOBILE RADIO TERMINAL EQUIPMENT
Next Patent: PORTABLE MOBILE RADIO TERMINAL EQUIPMENT