Title:
POLYPHASE CLOCK GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JP2994272
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the dispersion in the duty of an internal clock of the clock generating circuit and to set the duty.
SOLUTION: The leading edge of internal clocks C1, C2 is synchronized with the trailing edge of an output signal CA of a PLL circuit 1, and the trailing edge of the clock signals is synchronized with an output signal CB of a frequency divider circuit 2 synchronously with the rising edge of an output signal CA of the PLL circuit 1 so as to eliminate overlapping between internal clock signals and the internal clock with small dispersion in the duty is obtained.
Inventors:
Yasuo Sugazawa
Application Number:
JP22224896A
Publication Date:
December 27, 1999
Filing Date:
August 23, 1996
Export Citation:
Assignee:
Kyushu NEC Corporation
International Classes:
H03K21/10; G06F1/06; H03K5/15; H03L7/08; H04L7/033; (IPC1-7): H03K5/15; H03K21/10; H03L7/08
Domestic Patent References:
| JP6131074A | ||||
| JP6209243A |
Other References:
【文献】米国特許5341031(US,A)
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)