Title:
DATA BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JP2018200574
Kind Code:
A
Abstract:
To provide a data buffer circuit of the present invention capable of reading the most recent data at an arbitrary timing.SOLUTION: A data buffer circuit 1 includes a data strobe signal generation circuit 11 provided in an internal interface unit 90 for generating a data strobe signal synchronized with an interface clock signal, an asynchronous signal synchronizing circuit 13 for synchronizing the data strobe signal with an operation clock signal that is higher in frequency than the interface clock signal, a data hold circuit having a D-latch 15a provided with an input terminal to which a data signal synchronized with the operation clock signal is input and a control signal input terminal to which an output signal of the asynchronous signal synchronizing circuit 13 is input, and a data receiving circuit 17 to which an output signal from the data holding circuit 15 provided in the internal interface unit 90 is input to sample by the interface clock signal.SELECTED DRAWING: Figure 1
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Inventors:
YOKOBORI TAKUMI
TSUJI SHINSUKE
TSUJI SHINSUKE
Application Number:
JP2017104965A
Publication Date:
December 20, 2018
Filing Date:
May 26, 2017
Export Citation:
Assignee:
ASAHI KASEI DENSHI KK
International Classes:
G06F1/12; H04L7/00
Attorney, Agent or Firm:
Tetsuya Mori
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