Title:
DATA PROCESSING CIRCUIT
Document Type and Number:
Japanese Patent JP3396067
Kind Code:
B2
Abstract:
PURPOSE: To provide a data processing circuit which improves demodulation reliability by eliminating the influence of echo and same-channel disturbance when a bit flow is demodulated.
CONSTITUTION: To expand the eye aperture of a series data signal (e.g. teletext signal), the data signal is supplied to a track hold circuit (2) of the data processing circuit, and then a positive peak value and a negative peak value of the data signal are held alternately. For the purpose, the data processing circuit is equipped with a means (3) which detects the generation of a peak value and a means (4) which detects whether or not the data signal crosses a tentative slice level. A control circuit (7) switches the detection from the positive peak value to the negative peak value and vice versa.
Inventors:
Johannes Joseph Francis Cass Rains
Application Number:
JP26116493A
Publication Date:
April 14, 2003
Filing Date:
October 19, 1993
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
H04N5/445; H04L7/02; H04L25/03; H04L25/06; H04N7/00; H04N7/025; H04N7/03; H04N7/035; H04N7/08; H04L7/033; (IPC1-7): H04N7/025; H04L25/03; H04N7/03; H04N7/035
Domestic Patent References:
| JP58130675A | ||||
| JP1236748A | ||||
| JP58215837A | ||||
| JP5772481A | ||||
| JP626396B2 |
Attorney, Agent or Firm:
Akihide Sugimura (5 outside)