Title:
DATA TRANSFER SYSTEM
Document Type and Number:
Japanese Patent JP3420114
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve the data transfer speed in a single mode without deteriorating the data transfer speed of a burst mode.
SOLUTION: When a read access is given from a PCI(peripheral component interconnect/interface) bus 21, a PCI interface 12 decides whether the read access is single or burst read access. If a burst read access is decided, the interface 12 requests a memory interface 14 to return the read data in a synchronous transfer mode. Meanwhile, the interface 12 requests the interface 14 to return the read data in an asynchronous transfer mode in a single read access mode. In the synchronous transfer mode, the interface 12 fetches each of data from an internal bus and temporarily stores it for the clock switching and then outputs the data to the bus 21.
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Inventors:
Nakamukai Masafumi
Masaharu Ejiri
Masaharu Ejiri
Application Number:
JP15966999A
Publication Date:
June 23, 2003
Filing Date:
June 07, 1999
Export Citation:
Assignee:
NEC
Kyushu NEC Corporation
Kyushu NEC Corporation
International Classes:
G06F13/16; G06F12/00; G06F12/02; G06F13/28; G06F13/36; G06F13/42; H04L29/10; (IPC1-7): G06F13/36; G06F13/16; G06F13/28; G06F13/42
Domestic Patent References:
| JP6159563A | ||||
| JP63113750A | ||||
| JP512197A | ||||
| JP9282274A | ||||
| JP1139257A |
Attorney, Agent or Firm:
Rock wall Fuyuki