Title:
DECODER CIRCUIT
Document Type and Number:
Japanese Patent JP2963560
Kind Code:
B2
Abstract:
PURPOSE: To reduce the power consumption of a receiver by lowering a frequency of a system clock of a microprocessor mounted on a radio call receiver in a data communication.
CONSTITUTION: A base band signal detected by a radio receiving part 13 becomes an input signal, two data generating parts A 1, B 3, and two bit synchronizing circuits A 2, B 4 for giving a synchronizing clock to each of them are provided. synchronization of two bit synchronizing circuits A 2, B 4 is corrected by synchronizing information obtained by executing a synchronizing collation of reproducing data A from the data generating part A 1, and collecting information from a correcting storage circuit 6, and one of the reproducing data A and reproducing data B is selected by a selecting circuit 7, and thereafter, subjected to series conversion and becomes an output of a decoder circuit 14.
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Inventors:
HOSHI ATSUSHI
TAKAOKA YASUHARU
TAKAOKA YASUHARU
Application Number:
JP20564191A
Publication Date:
October 18, 1999
Filing Date:
July 23, 1991
Export Citation:
Assignee:
KOKUSAI DENKI KK
International Classes:
H03M9/00; H04L7/02; (IPC1-7): H04L7/02; H03M9/00
Domestic Patent References:
| JP57132244A | ||||
| JP6447133U |
Attorney, Agent or Firm:
Otsuka Manabu